    set sopc "c:/altera/quartus60/sopc_builder"
    set sopc_perl "c:/altera/quartus60//bin/perl561"
    echo "Sopc_Builder Directory: $sopc";

# ModelSimPE and OEM have different requirements
# regarding how they load their test bench.
# We account for that 
if { [ vsimAuth ] == "ALTERA" } {
 alias _init_setup {vlib work

                       vmap altera               work
                       vcom -93 -explicit c:/altera/quartus60/libraries/vhdl/altera/altera_europa_support_lib.vhd
		       } } else {
 alias _init_setup {vlib work

                       vmap lpm                  work
                       vmap altera               work
                       vmap altera_mf            work
                       vmap sgate_pack           work
                       vmap sgate                work
                       vcom -93 -explicit c:/altera/quartus60/libraries/vhdl/altera/altera_europa_support_lib.vhd
                       vcom -93 -explicit c:/altera/quartus60/eda/sim_lib/altera_mf_components.vhd
                       vcom -93 -explicit c:/altera/quartus60/eda/sim_lib/altera_mf.vhd
                       vcom -93 -explicit c:/altera/quartus60/eda/sim_lib/220pack.vhd
                       vcom -93 -explicit c:/altera/quartus60/eda/sim_lib/220model.vhd
                       vcom -93 -explicit c:/altera/quartus60/eda/sim_lib/sgate_pack.vhd
                       vcom -93 -explicit c:/altera/quartus60/eda/sim_lib/sgate.vhd
                       } } 


# ModelSimPE and OEM have different requirements
# regarding how they simulate their test bench.
# We account for that here
if { [ vsimAuth ] == "ALTERA" } {
 alias _vsim {vsim -t ps +nowarnTFMPC  -L lpm -L altera -L altera_mf -L sgate test_bench }  } else {
 alias _vsim {vsim -t ps +nowarnTFMPC test_bench }  } 

alias test_contents_files {if {[ file exists "contents_file_warning.txt" ]} { set ch [open "contents_file_warning.txt" r];  while { 1 } { if ([eof $ch]) {break}; gets $ch line; puts $line; }; close $ch; } }
alias s "_init_setup
vcom -93 -explicit C:/Temp/horus/LCD.vhd
vcom -93 -explicit C:/Temp/horus/CPU_test_bench.vhd
vcom -93 -explicit C:/Temp/horus/CPU_mult_cell.vhd
vcom -93 -explicit C:/Temp/horus/CPU_jtag_debug_module.vhd
vcom -93 -explicit C:/Temp/horus/CPU_jtag_debug_module_wrapper.vhd
vcom -93 -explicit C:/Temp/horus/CPU.vho
vlog C:/Temp/horus/Altera_UP_Avalon_to_External_Bus_Bridge.v
vcom -93 -explicit C:/Temp/horus/AVALON.vhd
vcom -93 -explicit C:/Temp/horus/JTAG.vhd
vcom -93 -explicit C:/Temp/horus/clock_0.vhd
vcom -93 -explicit C:/Temp/horus/SWITCHES.vhd
vcom -93 -explicit C:/Temp/horus/clock_1.vhd
vcom -93 -explicit C:/Temp/horus/KEYS.vhd
vcom -93 -explicit C:/Temp/horus/TIMER0.vhd
vcom -93 -explicit C:/Temp/horus/PLL.vhd
vcom -93 -explicit C:/Temp/horus/altpllPLL.vhd
vcom -93 -explicit C:/Temp/horus/IRDA.vhd
vcom -93 -explicit C:/Temp/horus/SDRAM.vhd
vcom -93 -explicit C:/Temp/horus/SDRAM_test_component.vhd
vcom -93 -explicit C:/Temp/horus/NIOS_II.vhd
_vsim
do virtuals.do
set StdArithNoWarnings 1
; test_contents_files"
alias r "exec $sopc_perl/bin/perl -I $sopc/bin/perl_lib -I $sopc/bin $sopc/bin/run_command_in_unix_like_shell.pl $sopc { cd ../;  ./NIOS_II_generation_script  } "
alias c "echo {Regenerating memory contents.
 (This may take a moment)...}; restart -f; exec $sopc_perl/bin/perl -I $sopc/bin/perl_lib -I $sopc/bin $sopc/bin/run_command_in_unix_like_shell.pl $sopc { cd ../;  ./NIOS_II_generation_script  }  --software_only=1"
alias w "do wave_presets.do"
alias l "do list_presets.do"
alias JTAG_log "./JTAG_log.bat $sopc_perl/bin &"
alias h "
echo @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
echo @@
echo @@        setup_sim.do
echo @@
echo @@   Defined aliases:
echo @@
echo @@   s  -- Load all design (HDL) files.
echo @@           re-vlog/re-vcom and re-vsim the design.
echo @@
echo @@   c  -- Re-compile memory contents.
echo @@          Builds C- and assembly-language programs
echo @@          (and associated simulation data-files
echo @@          such as UART simulation strings) for
echo @@          refreshing memory contents.
echo @@          Does NOT re-generate hardware (HDL) files
echo @@          ONLY WORKS WITH LEGACY SDK (Not the Nios IDE)
echo @@
echo @@   w  -- Sets-up waveforms for this design
echo @@          Each SOPC-Builder component may have
echo @@          signals 'marked' for display during
echo @@          simulation.  This command opens a wave-
echo @@          window containing all such signals.
echo @@
echo @@   l  -- Sets-up list waveforms for this design
echo @@          Each SOPC-Builder component may have
echo @@          signals 'marked' for listing during
echo @@          simulation.  This command opens a list-
echo @@          window containing all such signals.
echo @@
echo @@   JTAG_log  -- display interactive output window for JTAG

echo @@
echo @@   h  -- print this message 
echo @@
echo @@ ***Special VHDL settings***
echo @@    StdArithNoWarnings=1 in s command
echo @@"

h
